The backbone of many telecommunication networks is based on “packet switching systems”. Such systems comprise a large number of components referred to as “logic cards”. Logic cards control the flow of data “packets” through a network. It is essential that all logic cards within the same system be synchronized to one another. If they are not, packets may be lost leading to a resulting loss in data and information.
To ensure that this does not occur, logic cards within one packet switching system are designed to operate using the same timing frequency, e.g., 200 MHz. Because this frequency is central to the operation of an entire system it is referred to as a “master clock” frequency. Presently, this master clock frequency is itself derived from a “reference clock” frequency (e.g., 25 MHz). This reference frequency is generated by a so-called “clock card”.
During the lifetime of a packet switching system there will be a need to carry out maintenance or upgrades to the system, including to the clock card. In addition, clock cards sometimes fail. In either case, the result is that the clock card must be taken out of service.
It is essential that when a clock card is taken out of service that the logic cards are still fed a reference frequency (i.e., the 25 MHz signal mentioned above). If the logic cards do not receive the appropriate reference frequency, they will not be able to generate their own 200 MHz master clock frequencies. This in turn leads to an increased risk that packets of information or data will be lost. This scenario must be prevented at all costs.
One way of preventing such loss of data is to use two different clock cards. The thought behind this design is that when one clock card fails, or needs maintenance, it is disconnected from the logic cards and a second logic card is connected.
However, even though both clock cards are ideally designed to generate the same frequency, problems arise in making sure that the two reference frequencies stay within substantially the same frequency range and remain in phase (i.e., maintain the same timing) with one another over time.
Accordingly, it is desirable to provide techniques to ensure the proper synchronization of logic cards within a packet switching system when one or more clock cards are taken out of service.
Further desires of the present invention will become apparent from the drawings, detailed description of the invention and claims which follow.